The electronics industry is under constant pressure to both reduce component size as well as power requirements and has a market driven need to improve operation of memory devices. One approach to reduce component size is to fabricate devices in a three-dimensional (3D) configuration. For example, a memory device can be arranged as a stack of memory cells vertically on a substrate. Such memory cells can be implemented as charge trap cells. Improvements to charge trap based memory devices and their operation can be addressed by advances in design and processing of the memory devices.